The present invention relates to the field of current mirror circuits and more particularly to such circuits that are fabricated by using integrated circuit processes. The subject invention is a precision current mirror topology that provides improved performance over prior art. The subject invention provides improve precision in a switched current digital to analog converter (DAC) by reducing errors introduced by replicating currents.
In general, a current mirror is a circuit that produces an output current in response to a current applied to the input. The current mirror output replicates the input current, hence the term "current mirror". The current mirror is a basic analog building block. The current mirror is used in comparators, operational amplifiers, balanced modulators and many other circuit topologies.
The current mirror is also the basic circuit element of switched current digital to analog converters (DACs). The switched current DAC is a multiple output current mirror with an array of switch transistors that steer the mirror currents. By summing the mirror currents, the current steering DAC produces an output current that is proportional to the digital input code. As such, an invention that improves current mirror accuracy shall also produce improved precision in DACs.
FIG. 1 discloses a simple prior art current mirror circuit. FIG. 1 has an input terminal 114 for receiving an input current. The input current is often produced by another circuit or device that is either on or off the chip. FIG. 1 shows a first PMOS transistor 110 having a gate electrode connected to a gate common node 140, and also to the drain 112 of the first PMOS transistor 110. The common gate node 140 is also connected to the gate of a second PMOS transistor 120A and the gate of a third PMOS transistor 120B. The drain 122A of the second PMOS transistor 120A is connected to a first output terminal 124A of the current mirror. The drain 122B of third PMOS transistor 120B is connected to a second output terminal 124B of the current mirror.
A first output load 128A is connected to the first output terminal 124A of the current mirror circuit. A second output load 128B is also connected to the second output terminal 124B of the current mirror circuit. In addition, the source electrodes of the PMOS transistors 110, 120A and 120B are connected to a common voltage node AVDD.
For the sake of the present discussion, the electrical parameters of all three PMOS transistors 110, 120A and 120B shall be considered equal or matched. In addition all three devices are long channel devices operated in the "saturated square law region". Under these assumptions, the drain current of a MOS transistor is independent of the drain voltage. The drain current Id is then only a function of the gate to source voltage. As such this "ideal" current mirror produces output currents I1 and I2 that are equal to the applied input current Iin.
The current mirror of FIG. 1 performs the following operations. The input current, Iin is converted to a common gate to source voltage, Vgs at the common gate node 140 by the diode connected PMOS transistor 110. The common gate voltage Vgs is applied to the gate electrodes of PMOS transistors 120A and 120B. As such PMOS transistors 120A and 120B produce drain currents I1 and I2. EQU Vgsin=F (Iin) (1) EQU Vgs1=Vgs2=Vgsin (2) EQU Id=F.sup.-1 (Vgs) (3) EQU I1=I2=F.sup.-1 (Vgsin)=Iin (4)
In equation (1), the gate to source voltage Vgsin is produced by the transfer function F. Equation (2) shows that the gate to source voltage Vgs1 and Vgs2 are equal to Vgsin, which results from connecting the gates of PMOS transistors 110, 120A and 120B to the common gate node 140. Equations (3) show that the drain current Id is the inverse operation or inverse function of F, denoted as F.sup.-1 of Vgs. Equation (4) shows that mirror output currents I1 and I2 are both equal to the current mirror input current.
Once again it must be emphasized that equations (1), (2), (3) and (4) are only ideal relationships that are unobtainable under realistic conditions. They are only intended to show here that the current mirror converts the input current to voltage, and then that voltage is used to replicate the input current. If all electrical parameters of PMOS devices 110, 120A and 120B were identical and the effective drain impedances were infinite, then equations (1), (2) (3) and (4) would be valid and the output currents I1 and I2 would be identical to the input current Iin.
In reality the current mirror of FIG. 1 is fabricated with real devices which limit performance. The MOS transistor has a finite drain impedance when operated in the "saturated square law region". When the drain voltage increases, the depletion region of the drain moves under the gate in the direction of the source. This region shall collect carriers and as such the effective gate length of the MOS device is shortened. This condition is often called "channel length modulation". As such the drain impedance is approximately proportional to the drain length and inversely proportional to the drain current of the MOS transistor.
Even with a gate length of 10 microns, it is not unusual for the output current of the mirror circuit of FIG. 1 to change 10 per cent as the output voltage changes by 2 volts.
In addition, the current mirror of FIG. 1 is sensitive to device mismatch in electrical parameters. In any fabrication process there must be some tolerance allowed in order to fabricate devices having an acceptable yield. The process tolerances produce variations in the device parameters. From lot to lot there is an allowed variance in key process parameters. For example oxide thickness of the MOS devices are plus or minus 10 per cent of the nominal value. As a consequence, there are also variations across a wafer, and across the integrated circuit device. In a typical CMOS or BICMOS process some parameters match very well and some parameters do not.
For a long channel MOS transistor, operated in the "saturated square law region", the drain current Id is predicted as: EQU Id=K' W/L [Vgs-Vt].sup.2 (5)
where, K' and Vt are process dependent parameters.
The drain current Id is a function of process dependent parameters K' and the MOS threshold voltage Vt. The parameter K' is a function of the insulator material (gate oxide) and is inversely proportional to the oxide thickness. In addition, K' is also a function of the semiconductor mobility, which in turn is dependent on the impurity concentration. The MOS threshold voltage is dependent on the oxide thickness, the carrier concentration, the material used for the gate electrode and the density of interface states at the gate oxide to semiconductor interface.
For a typical CMOS process, K' has a lot to lot tolerance of +/-10 per cent of its nominal value. The MOS threshold voltage has a lot to lot tolerance of about 0.1 volts to 0.2 volts of the nominal value. Upon the same integrated circuit device, K' shall exhibit a variation of perhaps 0.5 per cent, and Vt shall exhibit a variation of +/-0.02 volts. Even "matched" MOS devices in close proximity exhibit a 0.01 volt Vt mismatch.
In addition the channel width W and gate length L shall also exhibit variations due to processing tolerances, even on the same integrated circuit. By design, the variation in drain current due to variations in W and L are minimized by designing devices with large W and L. As such, 0.1 micron mismatch in L shall produce a variation of about 1 per cent in the drain current for a MOS device having a design length of 10 microns. Penalties result from the design of large devices. First, the capacitance shall increase, which limits the operating frequency. Second, area increases which shall increase the cost of the integrated circuit.
To evaluate the mismatch in drain current, equation (5) is evaluated using two MOS transistors having anticipated mismatches. The drain current Iin of a first MOS transistor and the drain current Iout of a second MOS are evaluated. The error is determined as: EQU error=[Iout/Iin-1] (6)
Equation (6) shows positive error for the current mirror output when Iout is greater than Iin. Likewise, the current mirror error is negative when Iout is less than Iin.
Substituting the corresponding parameters for the first and second MOS transistors of equation (5) into equation (6) the following equation occurs. ##EQU1## To represent a typical CMOS process, the following parametric values were selected. ##EQU2## For these selected parameters the anticipated error is 5.0 per cent. As W and L increase, the anticipated error approaches a limit of 2.5 per cent.
For most CMOS processes, the dominate error term of equation (7) is the MOS threshold voltage mismatch, Vt2-Vt1. In this example the threshold voltage mismatch contributes 2.1 per cent. The error due to threshold voltage mismatch is: ##EQU3## It is observed that the error of Vt mismatch decreases as Vgs-Vt increases. However, increasing Vgs-Vt requires more power supply voltage or limits the maximum output voltage of the current mirror output.
The current mirror circuit shown in FIG. 2, labeled prior art, provides increased drain impedance to improve performance over the circuit shown by FIG. 1. The current mirror of FIG. 2. includes a diode connected MOS transistor 210 with a drain connected to a common gate node 240. The current mirror circuit also includes MOS transistors 220A and 220B that produce drain currents at drain electrodes 222A and 222B respectively. Each MOS transistors 220A and 220B produce a a drain current in response to the voltage applied at the common gate node 240.
The current mirror of FIG. 2 also includes MOS transistors 226A and 226B. These MOS transistors are connected to form a cascode topology. MOS transistor 226A has source connected to the drain of current mirror MOS transistor 222A. Likewise, MOS transistor 226B has a source connected to the current mirror MOS transistor 222B. The gates of both MOS transistors 226A and 226B are connected to a bias circuit 290 that provides a bias voltage. The drains of the MOS transistors 226A and 226B are connected to the respective output loads.
In FIG. 2 both MOS transistors 222A and 222B produce a low source impedance to the drains of current mirror transistors 222A and 222B respectively. As such, a change in load voltage at the drains of MOS transistors 226A and 226B produces a much smaller change in voltage at the drains of MOS transistors 222A and 222B respectively.
The circuit of FIG. 2 provides improved performance over FIG. 1 because the change in the load voltage produces only a very small change in the current mirror output current. This circuit is often referred to as a "cascoded current mirror".
Although the circuit of FIG. 2 overcomes one serious limitation of FIG. 1, a major limitation remains in the circuit of FIG. 2. The circuit of FIG. 2 does not solve or improve upon the error due to device mismatch.
FIG. 3, which is labeled prior art, discloses a circuit that reduces the error due to device mismatch under certain conditions. FIG. 3 shows a current mirror that includes MOS transistors 310, 320A and 320B. MOS transistor 310 is connected as a diode, having the drain connected to the gate, which is also connected to the common gate node 340. In addition, FIG. 3 includes the resistors 316, 326A and 326B which are each connected to the source of the corresponding MOS transistor. The drain 312 of MOS transistor 310 is connected to the source of input current 318. The drain 322A of MOS transistor 320A and the drain 322B of MOS transistor of 320B are each connected to a corresponding output load.
In FIG. 3 MOS transistors 310, 320A and 320B are operated in the saturated region. In addition, it is assumed that a significant voltage occurs across the three resistors 316, 326A and 326B. As such, device mismatch in K', W, L or Vt shall produce a mismatch in the corresponding gate to source voltage. As such, a corresponding change in voltage shall occur across the corresponding resistor. For example, let the input current Iin be such that 1.0 volts occurs across the resistor 316. A mismatch in device parameters produces a mismatch in gate to source voltage between MOS transistors 310 and 320A. The mismatch in voltage shall then occur across resistor 326A, in addition to the voltage across the resistor 316. In this case a mismatch of 0.01 volts produces an error of less than 1.0 per cent. In the circuit of FIG. 1 the equivalent error was: EQU error=2 (Vt1-Vt2)/(Vgs1-Vt) (8)
An error in Vt of 0.01 volts produces an error of 2 per cent when Vgs-Vt is 1 volt. As such the circuit of FIG. 3 provides certain advantages. The voltage across the resistor in FIG. 3 is more than twice as effective as the gate to source voltage of FIG. 1 in improving accuracy. Therefore, a larger voltage is available at the current mirror output for a given accuracy. The resistor connected to the source of the MOS transistor of the current mirror output increases the output impedance. This reduces the sensitivity to the current mirror output voltage.
The current mirror of FIG. 3 improves accuracy by increasing the output impedance and by reducing sensitivity to device mismatch. This improved accuracy occurs with certain disadvantages and limitations. The current mirror of FIG. 3. requires a resistor for each current mirror output. For small currents large resistors are required to to improve accuracy. The resistors must have large values for both length and width so that the resistors match. These resistors often require large chip area. Over process and temperature the sheet resistance shall vary, which imposes a minimum and maximum voltage across the resistor for a specific input current. At one extreme, a maximum error occurs. At the other extreme, the output voltage range is limited. The circuit of FIG. 3 provides improved matching only over limited range of current. If the current is too small, the circuit becomes sensitive to device mismatches. When current is too large, insufficient supply voltage exists to drive the output load.
A switched current digital to analog converter (DAC) often comprises an array of current mirror outputs that are switched to a output node. Such a circuit is described in detail in U.S. Pat. No. 5,017,919 which is hereby incorporated by reference in its entirety. The accuracy of a switched current DAC is dependent on the accuracy of replicating currents. As such, the DAC produces various accuracy errors that are directly dependent on device mismatches.
Certain DAC specifications describe these accuracy errors. These include RESOLUTION, DNL, INL, FULL SCALE ERROR and THD. RESOLUTION is the number of code bits of the DAC. To obtain higher resolution on a DAC the DNL error must decrease. Otherwise, the DAC will exhibit non-monotonic behavior. DNL is the differential non-linearity error. This specification describes the consistency of the DAC output from a specified code step, to the next code step. The INL is the intergral non-linearity error. This term describes the worst case cumulative error of the DAC over all codes from a straight line. The FULL SCALE ERROR is the difference between measured full scale output and the ideal full scale output. THD is the total harmonic distortion. THD is the total distortion the DAC produces in replicating a sinusoidal waveform. THD is a function of DNL, INL and quantization error.
All of these accuracy specifications of a switched current DAC depend on the mismatch of the output current elements. As such these specifications depend on the matching accuracy of the current mirror structures of the DAC. The current mirror matching accuarcy depends on the musmatch in device parameters and on circuit topology. Improving the matching accuracy of the current mirrors of the switched current DAC improves the accuracy performance of the DAC.
The current mirror structures disclosed in FIG. 1, FIG. 2 and FIG. 3 have mismatch errors. As such, the mismatch in current shall contribute to DNL, INL, FULL SCALE ERROR and THD. The DNL results from the mismatch of current in current mirror elements and from the mismatch in current of binary weighted current structures. The INL results from DNL and from the mismatch of current mirror elements due to process gradients. The FULL SCALE ERROR results from a mismatch of the mirror input reference to the average of current mirror elements.
In switched current DACs the DNL is reduced by using fully decoded switch current elements. The fully decoded structure has an advantage that the current mirror mismatch error is not amplified by the binary weighted ratio. However, the fully decoded structure requires a much larger number of current mirror stages and the decoding logic to decode the binary weighted input. As resolution of the DAC increases it becomes essential to use fully decoded structures to keep the DNL error less than 1 LSB. However, as resolution increases it becomes essential to use binary weighted structures to keep the circuit complexity reasonable. For a fully decoded structure increasing the resolution by 1 bit doubles the circuit complexity and chip area.
It is therefore observed that the mismatch error of current mirror circuits produces numerous adverse effects. To obtain a specified accuracy, large geometry devices must be used. In addition, to obtain improved accuracy additional circuit elements must be used such as cascode devices and resistors. The additional circuit elements shall require an increase in chip area and cost. Often, the required accuracy is only obtained under limited operating ranges of output voltage and current.
As such, a current mirror topology having improved accuracy shall reduce chip area and cost while enhancing the circuit performance in the application employed. The claimed invention provides a current mirror circuit that reduces the mismatch error thereby improving the performance within the applications.